Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of doped monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. In a conventional semiconductor device 100 illustrated in FIG. 1, p-type substrate 1 is provided with field oxide 2 for isolating an active region comprising N+ source/drain regions 3, and a gate electrode 4, typically of doped polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric layer 6, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer 8, typically of aluminum or an aluminum-base alloy, and source/drain regions 3 through contacts 7, and to transistor gate electrode 49. Dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 1, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer 13 deposited thereon. Protective dielectric layer 13 typically comprises a nitride layer, such as silicon nitride (Si.sub.3 N.sub.4). Alternatively, protective dielectric layer 13 may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer 13 provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer 13, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection by means of bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are depicted in FIG. 1 for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g. five conductive metal layers. Also in the interest of illustrative convenience, FIG. 1 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
Hydrogen is typically employed during several steps in the manufacturing of conventional semiconductor device 100. For example, during annealing of semiconductor device 100 after dielectric layer 13 is deposited, the furnace atmosphere often contains hydrogen. Hydrogen atoms from the furnace atmosphere diffuse through the semiconductor device and bond with "dangling", i.e., unbonded, silicon atoms at the interface between substrate 1 and gate oxide 5.
In semiconductor devices, particularly devices with design features of 0.25 microns and under, device performance degrades over time due to "hot carrier" effects. Hot carrier degradation occurs when the electric field generated by the supply voltage of the semiconductor device makes it possible for electrons at the transistor level to gain sufficient energy to be injected onto gate oxide 5, typically silicon dioxide (SiO.sub.2). These "hot electrons" stimulate the desorption of hydrogen from the Si/SiO.sub.2 interface of substrate 1 and gate oxide 5, by breaking hydrogen/silicon bonds. Over time, the silicon substrate 1 and gate oxide 5 become charged, thereby changing the electrical properties of the transistor. For example, the transistor threshold voltage may be raised and the transconductance reduced, thereby degrading the performance of the transistor.
One prior approach for reducing the hot carrier effects comprises annealing in a deuterium atmosphere after deposition of protective dielectric layer 13. Since deuterium atoms are heavier than hydrogen atoms, deuterium/silicon bonds are more difficult to break by hot electrons than the hydrogen/silicon bonds.
A drawback attendant upon introducing deuterium at the final annealing step is that the deuterium atoms may not diffuse through topside dielectric layer 13, typically a silicon nitride layer, quickly enough to reach the dangling silicon bonds at the Si/SiO.sub.2 interface. Therefore, introducing deuterium at the final annealing step is often ineffective in passivating the dangling silicon bonds. If the temperature of the furnace is increased, to increase the rate of diffusion of the deuterium atoms through protective dielectric layer 13 and through the various metal and dielectric layers to the Si/SiO.sub.2 interface, the metal layers as well as other previously defined layers can break down. Additionally, increasing the annealing time to allow the deuterium more time to diffuse to the Si/SiO.sub.2 interface adds additional cost to the annealing process.
Therefore, a need exists for semiconductor methodology enabling reduction of hot carrier degradation. A particular need exists for semiconductor methodology enabling reduction of hot carrier effects without increasing the annealing time or temperature.